spinnaker.h

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//------------------------------------------------------------------------------
// Email:            steven.temple@manchester.ac.uk
//
//------------------------------------------------------------------------------
 
/*
 * Copyright (c) 2009 The University of Manchester
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 
#ifndef __SPINNAKER_H__
#define __SPINNAKER_H__
 
//------------------------------------------------------------------------------
 
// Type definitions for unsigned integers
 
typedef unsigned char uchar;        
typedef unsigned short ushort;      
typedef unsigned int uint;          
typedef unsigned long long uint64;  
 
// Used in register offset definitions below
#define INT_AT(t) ((t) / 4)
 
// Miscellaneous...
 
#ifndef NULL
#define NULL            0           
#endif
 
#define BIT_31          0x80000000  
 
 
#define BUF_WRITE       1
 
//------------------------------------------------------------------------------
 
// Numbers of CPUS, links
 
#define NUM_CPUS        18      
#define NUM_LINKS       6       
 
//------------------------------------------------------------------------------
 
 
#define ITCM_BASE           0x00000000
#define ITCM_SIZE           0x00008000  // 32 KB
#define ITCM_TOP            (ITCM_BASE + ITCM_SIZE)
 
#define DTCM_BASE           0x00400000
#define DTCM_SIZE           0x00010000  // 64 KB
#define DTCM_TOP            (DTCM_BASE + DTCM_SIZE)
 
#define SDRAM_BASE_UNBUF    0x70000000
#define SDRAM_BASE_BUF      0x60000000
 
#ifdef BUF_WRITE
#define SDRAM_BASE          SDRAM_BASE_BUF
#else
#define SDRAM_BASE          SDRAM_BASE_UNBUF
#endif
 
#define SDRAM_SIZE          (128 * 1024 * 1024) // 128 MB
#define SDRAM_TOP           (SDRAM_BASE + SDRAM_SIZE)
 
#define SYSRAM_BASE_UNBUF   0xf5000000
#define SYSRAM_BASE_BUF     0xe5000000
 
#ifdef BUF_WRITE
#define SYSRAM_BASE         SYSRAM_BASE_BUF
#else
#define SYSRAM_BASE         SYSRAM_BASE_UNBUF
#endif
 
#define SYSRAM_SIZE         0x00008000  // 32 KB
#define SYSRAM_TOP          (SYSRAM_BASE + SYSRAM_SIZE)
 
#define ROM_BASE            0xf6000000
#define ROM_SIZE            0x00008000  // 32 KB
#define ROM_TOP             (ROM_BASE + ROM_SIZE)
 
//------------------------------------------------------------------------------
 
 
#define CC_BASE_UNBUF   0x10000000  // Unbuffered
#define CC_BASE_BUF     0x20000000  // Buffered
 
#ifdef BUF_WRITE
#define CC_BASE         CC_BASE_BUF
#else
#define CC_BASE         CC_BASE_UNBUF
#endif
 
#define CC_TCR          INT_AT(0x00)
#define CC_TXDATA       INT_AT(0x04)
#define CC_TXKEY        INT_AT(0x08)
#define CC_RSR          INT_AT(0x0c)
#define CC_RXDATA       INT_AT(0x10)
#define CC_RXKEY        INT_AT(0x14)
#define CC_SAR          INT_AT(0x18)
#define CC_TEST         INT_AT(0x1c)
 
//------------------------------------------------------------------------------
 
 
#define TIMER_BASE_UNBUF    0x11000000
#define TIMER_BASE_BUF      0x21000000
 
#ifdef BUF_WRITE
#define TIMER_BASE      TIMER_BASE_BUF
#else
#define TIMER_BASE      TIMER_BASE_UNBUF
#endif
 
#define TIMER_OFFSET    0x20        
 
#define TIMER1_BASE     (TIMER_BASE)
#define TIMER2_BASE     (TIMER_BASE + TIMER_OFFSET)
 
#define TC_LOAD         INT_AT(0x00)
#define TC_COUNT        INT_AT(0x04)
#define TC_CONTROL      INT_AT(0x08)
#define TC_INT_CLR      INT_AT(0x0c)
#define TC_RAW_INT      INT_AT(0x10)
#define TC_MASK_INT     INT_AT(0x14)
#define TC_BG_LOAD      INT_AT(0x18)
 
#define T1_LOAD         INT_AT(0x00)
#define T1_COUNT        INT_AT(0x04)
#define T1_CONTROL      INT_AT(0x08)
#define T1_INT_CLR      INT_AT(0x0c)
#define T1_RAW_INT      INT_AT(0x10)
#define T1_MASK_INT     INT_AT(0x14)
#define T1_BG_LOAD      INT_AT(0x18)
 
#define T2_LOAD         INT_AT(0x20)
#define T2_COUNT        INT_AT(0x24)
#define T2_CONTROL      INT_AT(0x28)
#define T2_INT_CLR      INT_AT(0x2c)
#define T2_RAW_INT      INT_AT(0x30)
#define T2_MASK_INT     INT_AT(0x34)
#define T2_BG_LOAD      INT_AT(0x38)
 
//------------------------------------------------------------------------------
 
 
#define VIC_BASE_UNBUF  0x1f000000
#define VIC_BASE_BUF    0x2f000000
 
#ifdef BUF_WRITE
#define VIC_BASE        VIC_BASE_BUF
#else
#define VIC_BASE        VIC_BASE_UNBUF
#endif
 
#define VIC_IRQST       INT_AT(0x00)
#define VIC_FIQST       INT_AT(0x04)
#define VIC_RAW         INT_AT(0x08)
#define VIC_SELECT      INT_AT(0x0c)
#define VIC_ENABLE      INT_AT(0x10)
#define VIC_DISABLE     INT_AT(0x14)
#define VIC_SOFT_SET    INT_AT(0x18)
#define VIC_SOFT_CLR    INT_AT(0x1c)
#define VIC_PROTECT     INT_AT(0x20)
#define VIC_VADDR       INT_AT(0x30)
#define VIC_DEFADDR     INT_AT(0x34)
 
#define VIC_ADDR        INT_AT(0x100)
 
#define VIC_ADDR0       INT_AT(0x100)
#define VIC_ADDR1       INT_AT(0x104)
#define VIC_ADDR2       INT_AT(0x108)
#define VIC_ADDR3       INT_AT(0x10c)
#define VIC_ADDR4       INT_AT(0x110)
#define VIC_ADDR5       INT_AT(0x114)
#define VIC_ADDR6       INT_AT(0x118)
#define VIC_ADDR7       INT_AT(0x11c)
#define VIC_ADDR8       INT_AT(0x120)
#define VIC_ADDR9       INT_AT(0x124)
#define VIC_ADDR10      INT_AT(0x128)
#define VIC_ADDR11      INT_AT(0x12c)
#define VIC_ADDR12      INT_AT(0x130)
#define VIC_ADDR13      INT_AT(0x134)
#define VIC_ADDR14      INT_AT(0x138)
#define VIC_ADDR15      INT_AT(0x13c)
 
#define VIC_CNTL        INT_AT(0x200)
 
#define VIC_CNTL0       INT_AT(0x200)
#define VIC_CNTL1       INT_AT(0x204)
#define VIC_CNTL2       INT_AT(0x208)
#define VIC_CNTL3       INT_AT(0x20c)
#define VIC_CNTL4       INT_AT(0x210)
#define VIC_CNTL5       INT_AT(0x214)
#define VIC_CNTL6       INT_AT(0x218)
#define VIC_CNTL7       INT_AT(0x21c)
#define VIC_CNTL8       INT_AT(0x220)
#define VIC_CNTL9       INT_AT(0x224)
#define VIC_CNTL10      INT_AT(0x228)
#define VIC_CNTL11      INT_AT(0x22c)
#define VIC_CNTL12      INT_AT(0x230)
#define VIC_CNTL13      INT_AT(0x234)
#define VIC_CNTL14      INT_AT(0x238)
#define VIC_CNTL15      INT_AT(0x23c)
 
enum spinnaker_interrupt_numbers_e {
    WDOG_INT = 0,       
    SOFTWARE_INT = 1,   
    COMM_RX_INT = 2,    
    COMM_TX_INT = 3,    
    TIMER1_INT = 4,     
    TIMER2_INT = 5,     
    CC_RDY_INT = 6,     
    CC_RPE_INT = 7,     
    CC_RFE_INT = 8,     
    CC_TFL_INT = 9,     
    CC_TOV_INT = 10,    
    CC_TMT_INT = 11,    
    DMA_DONE_INT = 12,  
    DMA_ERR_INT = 13,   
    DMA_TO_INT = 14,    
    RTR_DIAG_INT = 15,  
    RTR_DUMP_INT = 16,  
    RTR_ERR_INT = 17,   
    CPU_INT = 18,       
    ETH_TX_INT = 19,    
    ETH_RX_INT = 20,    
    ETH_PHY_INT = 21,   
    SLOW_CLK_INT = 22,  
    CC_TNF_INT = 23,    
    CC_MC_INT = 24,     
    CC_P2P_INT = 25,    
    CC_NN_INT = 26,     
    CC_FR_INT = 27,     
    INT0_INT = 28,      
    INT1_INT = 29,      
    GPIO8_INT = 30,     
    GPIO9_INT = 31,     
};
 
//------------------------------------------------------------------------------
 
 
#define DMA_BASE_UNBUF  0x30000000
#define DMA_BASE_BUF    0x40000000
 
#ifdef BUF_WRITE
#define DMA_BASE        DMA_BASE_BUF
#else
#define DMA_BASE        DMA_BASE_UNBUF
#endif
 
#define DMA_ADRS        INT_AT(0x04)
#define DMA_ADRT        INT_AT(0x08)
#define DMA_DESC        INT_AT(0x0c)
#define DMA_CTRL        INT_AT(0x10)
#define DMA_STAT        INT_AT(0x14)
#define DMA_GCTL        INT_AT(0x18)
#define DMA_CRCC        INT_AT(0x1c)
#define DMA_CRCR        INT_AT(0x20)
#define DMA_TMTV        INT_AT(0x24)
#define DMA_SCTL        INT_AT(0x28)
 
#define DMA_STAT0       INT_AT(0x40)
#define DMA_STAT1       INT_AT(0x44)
#define DMA_STAT2       INT_AT(0x48)
#define DMA_STAT3       INT_AT(0x4c)
#define DMA_STAT4       INT_AT(0x50)
#define DMA_STAT5       INT_AT(0x54)
#define DMA_STAT6       INT_AT(0x58)
#define DMA_STAT7       INT_AT(0x5c)
 
#define DMA_AD2S        INT_AT(0x104)
#define DMA_AD2T        INT_AT(0x108)
#define DMA_DES2        INT_AT(0x10c)
 
#define DMA_CRCT        INT_AT(0x180)
 
//------------------------------------------------------------------------------
 
 
#define PL340_BASE_UNBUF    0xf0000000
#define PL340_BASE_BUF      0xe0000000
 
#ifdef BUF_WRITE
#define PL340_BASE      PL340_BASE_BUF
#else
#define PL340_BASE      PL340_BASE_UNBUF
#endif
 
#define MC_STAT         INT_AT(0x00)
#define MC_CMD          INT_AT(0x04)
#define MC_DIRC         INT_AT(0x08)
#define MC_MCFG         INT_AT(0x0c)
 
#define MC_REFP         INT_AT(0x10)
#define MC_CASL         INT_AT(0x14)
#define MC_DQSS         INT_AT(0x18)
#define MC_MRD          INT_AT(0x1c)
#define MC_RAS          INT_AT(0x20)
#define MC_RC           INT_AT(0x24)
#define MC_RCD          INT_AT(0x28)
#define MC_RFC          INT_AT(0x2c)
#define MC_RP           INT_AT(0x30)
#define MC_RRD          INT_AT(0x34)
#define MC_WR           INT_AT(0x38)
#define MC_WTR          INT_AT(0x3c)
#define MC_XP           INT_AT(0x40)
#define MC_XSR          INT_AT(0x44)
#define MC_ESR          INT_AT(0x48)
 
#define MC_MCFG2        INT_AT(0x4c)
#define MC_MCFG3        INT_AT(0x50)
 
#define MC_QOS0         INT_AT(0x100)
#define MC_QOS1         INT_AT(0x104)
#define MC_QOS2         INT_AT(0x108)
#define MC_QOS3         INT_AT(0x10c)
#define MC_QOS4         INT_AT(0x110)
#define MC_QOS5         INT_AT(0x114)
#define MC_QOS6         INT_AT(0x118)
#define MC_QOS7         INT_AT(0x11c)
#define MC_QOS8         INT_AT(0x120)
#define MC_QOS9         INT_AT(0x124)
#define MC_QOS10        INT_AT(0x128)
#define MC_QOS11        INT_AT(0x12c)
#define MC_QOS12        INT_AT(0x130)
#define MC_QOS13        INT_AT(0x134)
#define MC_QOS14        INT_AT(0x138)
#define MC_QOS15        INT_AT(0x13c)
 
#define MC_CCFG0        INT_AT(0x200)
#define MC_CCFG1        INT_AT(0x204)
#define MC_CCFG2        INT_AT(0x208)
#define MC_CCFG3        INT_AT(0x20c)
 
#define DLL_STATUS      INT_AT(0x300)
#define DLL_CONFIG0     INT_AT(0x304)
#define DLL_CONFIG1     INT_AT(0x308)
 
//------------------------------------------------------------------------------
 
 
#define RTR_BASE_UNBUF  0xf1000000
#define RTR_BASE_BUF    0xe1000000
 
#ifdef BUF_WRITE
#define RTR_BASE        RTR_BASE_BUF
#else
#define RTR_BASE        RTR_BASE_UNBUF
#endif
 
#define RTR_CONTROL     INT_AT(0x00)
#define RTR_STATUS      INT_AT(0x04)
 
#define RTR_EHDR        INT_AT(0x08)
#define RTR_EKEY        INT_AT(0x0c)
#define RTR_EDAT        INT_AT(0x10)
#define RTR_ESTAT       INT_AT(0x14)
#define RTR_DHDR        INT_AT(0x18)
#define RTR_DKEY        INT_AT(0x1c)
#define RTR_DDAT        INT_AT(0x20)
#define RTR_DLINK       INT_AT(0x24)
#define RTR_DSTAT       INT_AT(0x28)
#define RTR_DGEN        INT_AT(0x2c)
 
// registers r12-r32 are NOT described here!
 
#define RTR_FR          INT_AT(0x84)
 
#define RTR_DGF0        INT_AT(0x200)
#define RTR_DGF1        INT_AT(0x204)
#define RTR_DGF2        INT_AT(0x208)
#define RTR_DGF3        INT_AT(0x20c)
#define RTR_DGF4        INT_AT(0x210)
#define RTR_DGF5        INT_AT(0x214)
#define RTR_DGF6        INT_AT(0x218)
#define RTR_DGF7        INT_AT(0x21c)
#define RTR_DGF8        INT_AT(0x220)
#define RTR_DGF9        INT_AT(0x224)
#define RTR_DGF10       INT_AT(0x228)
#define RTR_DGF11       INT_AT(0x22c)
#define RTR_DGF12       INT_AT(0x230)
#define RTR_DGF13       INT_AT(0x234)
#define RTR_DGF14       INT_AT(0x238)
#define RTR_DGF15       INT_AT(0x23c)
 
#define RTR_DGC0        INT_AT(0x300)
#define RTR_DGC1        INT_AT(0x304)
#define RTR_DGC2        INT_AT(0x308)
#define RTR_DGC3        INT_AT(0x30c)
#define RTR_DGC4        INT_AT(0x310)
#define RTR_DGC5        INT_AT(0x314)
#define RTR_DGC6        INT_AT(0x318)
#define RTR_DGC7        INT_AT(0x31c)
#define RTR_DGC8        INT_AT(0x320)
#define RTR_DGC9        INT_AT(0x324)
#define RTR_DGC10       INT_AT(0x328)
#define RTR_DGC11       INT_AT(0x32c)
#define RTR_DGC12       INT_AT(0x330)
#define RTR_DGC13       INT_AT(0x334)
#define RTR_DGC14       INT_AT(0x338)
#define RTR_DGC15       INT_AT(0x33c)
 
#define RTR_TST1        INT_AT(0xf00)
#define RTR_TST2        INT_AT(0xf04)
 
#define P2P_TABLE_SIZE  8192
#define MC_TABLE_SIZE   1024
 
#define MC_RAM_WIDTH    (NUM_CPUS + NUM_LINKS)
#define MC_RAM_MASK     ((1 << MC_RAM_WIDTH) - 1)
 
#define MC_CORE_ROUTE(x)   (1 << ((x) + NUM_LINKS))
#define MC_LINK_ROUTE(x)   (1 << (x))
 
#define P2P_EPW         8           
#define P2P_LOG_EPW     3           
#define P2P_EMASK       (P2P_EPW-1) 
#define P2P_BPE         3           
#define P2P_BMASK       7           
 
#define P2P_INIT        0x00db6db6
 
#define RTR_MCRAM_BASE      (RTR_BASE + 0x00004000)
#define RTR_MCRAM_TOP       (RTR_MCRAM_BASE + MC_TABLE_SIZE * 4)
 
#define RTR_MCKEY_BASE      (RTR_BASE + 0x00008000)
#define RTR_MCKEY_TOP       (RTR_MCKEY_BASE + MC_TABLE_SIZE * 4)
 
#define RTR_MCMASK_BASE     (RTR_BASE + 0x0000c000)
#define RTR_MCMASK_TOP      (RTR_MCMASK_BASE + MC_TABLE_SIZE * 4)
 
#define RTR_P2P_BASE        (RTR_BASE + 0x00010000)
#define RTR_P2P_TOP         (RTR_P2P_BASE + P2P_TABLE_SIZE * 4)
 
#define MC_CAM_WIDTH        32
 
//------------------------------------------------------------------------------
 
 
#define SYSCTL_BASE_UNBUF   0xf2000000
#define SYSCTL_BASE_BUF     0xe2000000
 
#ifdef BUF_WRITE
#define SYSCTL_BASE     SYSCTL_BASE_BUF
#else
#define SYSCTL_BASE     SYSCTL_BASE_UNBUF
#endif
 
#define SC_CODE         0x5ec00000
 
#define CHIP_ID_CODE    0x59111012
 
#define SC_CHIP_ID      INT_AT(0x00)
#define SC_CPU_DIS      INT_AT(0x04)
#define SC_SET_IRQ      INT_AT(0x08)
#define SC_CLR_IRQ      INT_AT(0x0c)
#define SC_SET_OK       INT_AT(0x10)
#define SC_CPU_OK       INT_AT(0x10)
#define SC_CLR_OK       INT_AT(0x14)
 
#define SC_SOFT_RST_L   INT_AT(0x18)
#define SC_HARD_RST_L   INT_AT(0x1c)
#define SC_SUBS_RST_L   INT_AT(0x20)
 
#define SC_SOFT_RST_P   INT_AT(0x24)
#define SC_HARD_RST_P   INT_AT(0x28)
#define SC_SUBS_RST_P   INT_AT(0x2c)
 
#define SC_RST_CODE     INT_AT(0x30)
#define SC_MON_ID       INT_AT(0x34)
 
#define SC_MISC_CTRL    INT_AT(0x38)
 
#define GPIO_RES        INT_AT(0x3c)
 
#define GPIO_PORT       INT_AT(0x40)
#define GPIO_DIR        INT_AT(0x44)
#define GPIO_SET        INT_AT(0x48)
#define GPIO_CLR        INT_AT(0x4c)
#define GPIO_READ       INT_AT(0x48)
 
#define SC_PLL1         INT_AT(0x50)
#define SC_PLL2         INT_AT(0x54)
 
#define SC_FLAG         INT_AT(0x58)
#define SC_SETFLAG      INT_AT(0x58)
#define SC_CLRFLAG      INT_AT(0x5c)
 
#define SC_CLKMUX       INT_AT(0x60)
#define SC_SLEEP        INT_AT(0x64)
 
#define SC_TS0          INT_AT(0x68)
#define SC_TS1          INT_AT(0x6c)
#define SC_TS2          INT_AT(0x70)
 
#define SC_ARB0         INT_AT(0x080)
#define SC_TAS0         INT_AT(0x100)
#define SC_TAC0         INT_AT(0x180)
 
#define SC_LINK_DIS     INT_AT(0x200)
 
enum {
    RST_POR =       0, 
    RST_WDT =       1, 
    RST_USER =      2, 
    RST_SW =        3, 
    RST_WDI =       4  
};
 
//------------------------------------------------------------------------------
 
 
#define WDOG_BASE_UNBUF     0xf3000000
#define WDOG_BASE_BUF       0xe3000000
 
#ifdef BUF_WRITE
#define WDOG_BASE       WDOG_BASE_BUF
#else
#define WDOG_BASE       WDOG_BASE_UNBUF
#endif
 
#define WD_LOAD         INT_AT(0x00)
#define WD_COUNT        INT_AT(0x04)
#define WD_CTRL         INT_AT(0x08)
#define WD_INTCLR       INT_AT(0x0c)
#define WD_RAWINT       INT_AT(0x10)
#define WD_MSKINT       INT_AT(0x14)
#define WD_LOCK         INT_AT(0xc00)
 
#define WD_CODE         0x1acce551
 
enum {
    WD_INT_B = 1, 
    WD_RST_B = 2  
};
 
//------------------------------------------------------------------------------
 
 
#define ETH_BASE_UNBUF      0xf4000000
#define ETH_BASE_BUF        0xe4000000
 
#ifdef BUF_WRITE
#define ETH_BASE        ETH_BASE_BUF
#else
#define ETH_BASE        ETH_BASE_UNBUF
#endif
 
#define ETH_TX_BASE     (ETH_BASE + 0x0000)
#define ETH_TX_SIZE     0x0600
#define ETH_TX_TOP      (ETH_TX_BASE + ETH_TX_SIZE)
 
#define ETH_RX_BASE     (ETH_BASE + 0x4000)
#define ETH_RX_SIZE     0x0c00
#define ETH_RX_TOP      (ETH_RX_BASE + ETH_RX_SIZE)
 
#define ETH_RX_DESC_RAM (ETH_BASE + 0x8000)
#define ETH_REGS        (ETH_BASE + 0xc000)
 
#define ETH_CONTROL     INT_AT(0x00)
#define ETH_STATUS      INT_AT(0x04)
#define ETH_TX_LEN      INT_AT(0x08)
#define ETH_TX_CMD      INT_AT(0x0c)
#define ETH_RX_CMD      INT_AT(0x10)
#define ETH_MAC_LO      INT_AT(0x14)
#define ETH_MAC_HI      INT_AT(0x18)
#define ETH_PHY_CTRL    INT_AT(0x1c)
#define ETH_INT_CLR     INT_AT(0x20)
#define ETH_RX_BUF_RP   INT_AT(0x24)
#define ETH_RX_DESC_RP  INT_AT(0x2c)
 
enum {
    ETH_TX_CLR =    0x01, 
    ETH_RX_CLR =    0x10  
};
 
enum {
    PHY_CTRL_NRST =     1, 
    PHY_CTRL_DIN =      2, 
    PHY_CTRL_DOUT =     4, 
    PHY_CTRL_OE =       8, 
    PHY_CTRL_CLK =     16  
};
 
//------------------------------------------------------------------------------
 
 
static volatile uint * const cc  = (uint *) CC_BASE;
static volatile uint * const tc  = (uint *) TIMER_BASE;
static volatile uint * const tc1 = (uint *) TIMER1_BASE;
static volatile uint * const tc2 = (uint *) TIMER2_BASE;
static volatile uint * const vic = (uint *) VIC_BASE_UNBUF; // NB unbuffered
static volatile uint * const dma = (uint *) DMA_BASE;
 
static volatile uint * const sc  = (uint *) SYSCTL_BASE;
static volatile uint * const rtr = (uint *) RTR_BASE;
static volatile uint * const er  = (uint *) ETH_REGS;
static volatile uint * const mc  = (uint *) PL340_BASE;
static volatile uint * const wd  = (uint *) WDOG_BASE;
 
static uint * const sdram        = (uint *) SDRAM_BASE;
static uint * const sysram       = (uint *) SYSRAM_BASE;
 
static uint * const rtr_ram      = (uint *) RTR_MCRAM_BASE;
static uint * const rtr_key      = (uint *) RTR_MCKEY_BASE;
static uint * const rtr_mask     = (uint *) RTR_MCMASK_BASE;
static uint * const rtr_p2p      = (uint *) RTR_P2P_BASE;
 
static uchar * const eth_tx_ram  = (uchar *) ETH_TX_BASE;
static uchar * const eth_rx_ram  = (uchar *) ETH_RX_BASE;
static uint  * const eth_rx_desc = (uint *)  ETH_RX_DESC_RAM;
 
//------------------------------------------------------------------------------
 
 
enum {
    PKT_MC =        0x00000000, 
    PKT_P2P =       0x00400000, 
    PKT_NN =        0x00800000, 
    PKT_NND =       0x00a00000, 
    PKT_FR =        0x00c00000, 
 
    PKT_PL =        0x00020000, 
 
    PKT_MC_PL =     (PKT_MC + PKT_PL),  
    PKT_P2P_PL =    (PKT_P2P + PKT_PL), 
    PKT_NN_PL =     (PKT_NN + PKT_PL),  
    PKT_FR_PL =     (PKT_FR + PKT_PL)   
};
 
//------------------------------------------------------------------------------
 
 
#define CLK_XTAL_MHZ    10          
 
#define PLL_260         0x0007011a
#define PLL_300         0x0007011e
#define PLL_330         0x00070121
#define PLL_400         0x00070128
 
#define PLL_LOCK_TIME   80
 
#define PLL_CLK_SEL     0x809488a5  
 
//------------------------------------------------------------------------------
 
 
enum {
    SERIAL_NCS =    0x00000020, // Out
    SERIAL_CLK =    0x00000010, // Out
    SERIAL_SI =     0x00000008, // Out
    SERIAL_SO =     0x00000004, // In
 
    SERIAL_OE =     (SERIAL_NCS + SERIAL_CLK + SERIAL_SI)
};
 
#define TOP_BIT 0x80000000
#ifndef __GNUC__
// Don't warn out-of-int-range on armcc; uint is used anyway according to:
// https://developer.arm.com/documentation/dui0491/c/
// c-and-c---implementation-details/
// structures--unions--enumerations--and-bitfields?lang=en
#pragma push
#pragma diag_suppress 66
#endif
// On-chip SDRAM
enum {
    SDRAM_TQ =      TOP_BIT,
    SDRAM_DPD =     (1 << 30),
    SDRAM_HERE =    (1 << 29),
 
    JTAG_NTRST =    (1 << 27),
    JTAG_TMS =      (1 << 26),
    JTAG_TDI =      (1 << 25),
    JTAG_TCK =      (1 << 24)
};
#ifndef __GNUC__
// Undo suppression of warning
#pragma pop
#endif
 
enum {
    JTAG_RTCK =     (1 << 20), 
    JTAG_TDO =      (1 << 19), 
    JTAG_INT =      (1 << 15)  
};
 
// LEDs
 
#define LED_0           0x00000001  
 
//------------------------------------------------------------------------------
 
 
#define MODE_USER       0x10  
#define MODE_FIQ        0x11  
#define MODE_IRQ        0x12  
#define MODE_SVC        0x13  
#define MODE_ABT        0x17  
#define MODE_UND        0x1b  
#define MODE_SYS        0x1f  
 
#define THUMB_BIT       0x20  
 
#define IMASK_IRQ       0x80  
#define IMASK_FIQ       0x40  
#define IMASK_ALL       0xc0  
 
//------------------------------------------------------------------------------
 
#endif